The present invention relates to a wiring substrate and a semiconductor package, and more particularly to a wiring substrate having a solder resist layer constituted by a plurality of layers, as well as a semiconductor package having the same.
For example, in a semiconductor package in which a semiconductor chip is mounted on a wiring substrate having built-up wirings, a solder resist layer is formed as an outermost layer of the wiring substrate. A photo solder resist which is photosensitive is generally used as the solder resist layer. In addition, the solder resist layer is generally formed as a two-layered structure for forming a layer of a sufficient thickness.
FIG. 1 is a cross-sectional view partially illustrating a conventional semiconductor package. A semiconductor package 200 has a wiring substrate 100, a semiconductor chip 210, and an underfill resin 220. The wiring substrate 100 has an insulating layer 130, a wiring 140, a solder resist layer 150, and a metal layer 160. The solder resist layer 150 is constituted by two layers, an inner layer 150a and an outer layer 150b. The inner layer 150a and the outer layer 150b constituting the solder resist layer 150 contain a filler 170.
In the wiring substrate 100, the wiring 140 is formed on the insulating layer 130, and the solder resist layer having openings 150x for partially exposing the wiring 140 is further formed thereon. The metal layer 160 is formed in the openings 150x of the solder resist layer 150. The metal layer 160 is electrically connected to the wiring 140.
The semiconductor chip 210 has ball-like terminals 210a. In the semiconductor chip 210, a semiconductor integrated circuit (not shown) and electrode pads (not shown) are formed on a semiconductor substrate (not shown) formed of silicon or the like into a thin plate, and the ball-like terminals 210a serving as electrodes are formed on the electrode pads (not shown). The ball-like terminals 210a of the semiconductor chip 210 are electrically connected to the metal layer 160 of the wiring substrate 100. The underfill 220 is filled between the semiconductor chip 210 and the solder resist layer 150.
FIG. 2 is a cross-sectional view partially illustrating the semiconductor package shown in FIG. 1. In FIG. 2, those components that are identical to those shown in FIG. 1 will be denoted by the same reference numerals, and a description will be omitted in some cases. Reference character P1 denotes a shortest interval of the wiring 140. Symbol φ1 denotes the grain diameter of the filler 170. It should be noted that the grain diameter refers to a maximum grain diameter. Namely, the grain diameter refers to a longest portion in the dimensions of the filler. For example, if the filler is spherical, the grain diameter means its diameter, whereas if the cross section of the filler is elliptical, the grain diameter means its major axis. In addition, in a case where a plurality of fillers are present, the grain diameter refers to a maximum grain diameter among them.
The inner layer 150a and the outer layer 150b constituting the solder resist layer 150 contain the filler 170 with the grain diameter of φ1. The filler 170 is contained in the solder resist layer 150 for purposes of such as the optimization of the viscosity of the solder resist layer 150, improvement of its printability, improvement of its water resistance, and prevention of the occurrence of cracks. The grain diameter φ1 of the filler 170 is smaller than the shortest interval P1 of the wiring 140. The grain diameter φ1 of the filler 170 is, for example, 20 μm, and the shortest interval P1 of the wiring 140 is, for example, 30 μm (e.g., see patent document 1).    [Patent Document 1] JP-A-2000-31628
However, with increased miniaturization and thinning of the semiconductor package 200, the pitch of the wiring 140 is becoming narrow. FIG. 3 is a cross-sectional view illustrating a state in which the pitch of the wiring shown in FIG. 2 has become narrow. In FIG. 3, those components that are identical to those shown in FIG. 2 will be denoted by the same reference numerals, and a description will be omitted in some cases. Reference character P2 denotes a shortest interval of the wiring 140.
If the wiring 140 becomes increasingly narrower in pitch, the grain diameter φ1 of the filler 170 becomes larger than the shortest interval P2 of the wiring 140, so that there can be cases where the filler 170 is present at a position of being in contact with the wiring 140.
Incidentally, there are cases where water enters the solder resist layer 150 from the outside, if, in such a state, a voltage is applied to the wiring substrate 100 for constituting the semiconductor package 200, a so-called migration can possibly occur in which a metal such as Cu constituting the wiring 140 is ionized and recrystallized.
Since water is likely to enter the inner layer 150a through an interface between the filler 170 and the inner layer 150a, if the filler 170 is present at a position of being in contact with the adjacent wiring 140, the ionization of the metal such as Cu constituting the wiring 140 is accelerated when the migration has occurred. The ionized metal easily moves into the inner layer 150a along the interface between the filler 170 and the inner layer 150a and recrystallizes, so that the dielectric resistance between adjacent lines of the wiring 140 declines precipitously, leading to electrical shortcircuiting between the adjacent lines of the wiring 140.
Thus, in the wiring substrate 100 for constituting the conventional semiconductor package 200, there are cases where the grain diameter φ1 of the filler 170 contained in the solder resist layer 150 is larger than the shortest interval P2 of the wiring 140 covered by the solder resist layer 150. For this reason, there has been a problem in that the migration progresses due to the presence of the filler 170.
In addition, if the grain diameter φ1 of the filler 170 contained in the solder resist layer 150 is made smaller than the shortest interval P2 of the wiring 140 to overcome the above-described problem, there has been a problem in that it becomes impossible to attain the intended purposes of containing the filler 170, i.e., the optimization of the viscosity of the solder resist layer 150, improvement of its printability, improvement of its water resistance, and prevention of the occurrence of cracks.
The invention has been devised in view of the above-described circumstances, and its object is to provide a wiring substrate and a semiconductor package which are capable of preventing the progress of the migration while sufficiently attaining the intended purposes of containing the filler.
To attain the above object, according to a first aspect of the invention there is provided a wiring substrate including:
an insulating layer;
a wiring formed on the insulating layer; and
a solder resist layer formed on the insulating layer so as to cover at least a portion of the wiring, the solder resist layer being constituted by a plurality of layers, wherein
the plurality of layers contain fillers of different grain diameters,
a layer thickness of an innermost layer for constituting the plurality of layers is thicker than a layer thickness of the wiring, and
a grain diameter of the filler contained in the innermost layer is smaller than a shortest interval between adjacent lines of the wiring.
According to a second aspect, there is provided the wiring substrate according to the first aspect, wherein
the grain diameter of the filler contained in the innermost layer is smaller than the grain diameter of the filler contained in the other layers.
According to a third aspect, there is provided the wiring substrate according to the first or second aspect, wherein
an amount of the filler contained in the innermost layer is substantially identical to an amount of the filler contained in each of the other layers.
According to a forth aspect, there is provided the wiring substrate according to any one of the first to third aspects, wherein
the innermost layer is free of a secondary aggregation substance of the filler.
According to a fifth aspect, there is provided a wiring substrate including:
an insulating layer;
a wiring formed on the insulating layer; and
a solder resist layer formed on the insulating layer so as to cover at least a portion of the wiring, the solder resist layer being constituted by a plurality of layers, wherein
a layer thickness of an innermost layer for constituting the plurality of layers is thicker than a layer thickness of the wiring, and
the innermost layer is free of the filler.
According to a sixth aspect, there is provided a semiconductor package including:
the wiring substrate according to any one of first to fifth aspects, and
a semiconductor chip, wherein
the semiconductor chip is electrically connected to a portion of the wiring of the wiring substrate which is exposed from the solder resist layer.
According to a seventh aspect, there is provided a semiconductor package including:
an insulating layer;
a wiring formed on the insulating layer; and
a solder resist layer formed on the insulating layer so as to cover at least a portion of the wiring, the solder resist layer being constituted by a plurality of layers, wherein
the plurality of layers contain fillers of different grain diameters,
a layer thickness of an innermost layer for constituting the plurality of layers is thicker than a layer thickness of the wiring, and
a grain diameter of the filler contained in the innermost layer is smaller than a shortest interval between adjacent lines of the wiring.
According to an eighth aspect, there is provided the semiconductor package according to the seventh aspect, wherein
the grain diameter of the filler contained in the innermost layer is smaller than the grain diameter of the filler contained in the other layers.
According to a ninth aspect, there is provided the semiconductor package according to the seventh or eighth aspect, wherein
an amount of the filler contained in the innermost layer is substantially identical to an amount of the filler contained in each of the other layers.
According to a tenth aspect, there is provided the semiconductor package according to any one of the seventh to ninth aspects, wherein
the innermost layer is free of a secondary aggregation substance of the filler.
According to the invention, it is possible to provide a wiring substrate and a semiconductor package which are capable of preventing the progress of a migration while sufficiently attaining the intended purposes of containing the filler.